Heretofore, there have been proposed various types of fingerprint sensors. A typical one of them is shown in FIG. 1. The fingerprint sensor is generally indicated with a reference 110. The fingerprint sensor 110 includes a sensor cell 100 formed from an array of sense electrodes 101 laid on the surface of a semiconductor, a matrix of row select lines . . . , 102n−1, 102n, 102n+1, . . . and column sense lines . . . , 103m−1, 103m, 103m+1, . . . , positioned correspondingly to the sense electrodes 101, and cell select switches Sr connected between each of the sense electrodes 101 and column sense lines . . . , 103m−1, 103m, 103m+1, . . . . The cell select switches Sr are selected row by row via the row select lines . . . , 102n−1, 102n, 102n+1.
As shown in FIG. 2, when a finger F is placed on an overcoat 104 covering the sense electrodes 101 of the fingerprint sensor 110, a capacitance Cs develops between the sense electrode 101 and the surface Fn of the finger F correspondingly to irregularities of the fingerprint. The capacitance Cs is sensed to recognize a fingerprint pattern. More specifically, when a portion of the finger corresponding to a ridge portion of a fingerprint is on the sense electrode 101, the capacitance Cs developed between the sense electrode 101 and the finger surface will be large since the distance between the finger portion and the sense electrode 101 is short. On the other hand, when a portion of the finger corresponding to a valley portion of the fingerprint is on the sense electrode 101, the capacitance Cs will be small since the distance between the finger portion and the sense electrode 101 is long. Thus, by sensing the capacitance Cs, it is possible to recognize a pattern of the fingerprint. It should be noted that a capacitance Cp in FIG. 2 is a parasitic one between the sense electrode 101 and a Si (silicon) substrate.
To sense a capacitance Cs, it has been proposed to charge a capacitance Cs at a constant voltage and sense a charge stored in the capacitance Cs. This method is known as “voltage charging method”. Also, there has been proposed a method in which a constant charge is charged to the capacitance Cs and a voltage variation is sensed. This is known as “charge charging method”.
First, an example of the voltage charging method will be described with reference to the circuit diagram in FIG. 3 showing the principle of the method. The method will be described taking the circuitry of m columns shown in FIG. 1 by way of example.
As shown in FIG. 3, a sensing circuit 105m is connected to one end of each column sense line 103m in the m columns. The sensing circuit 105m includes an operational amplifier OP connected at the negative-phase (−) input terminal thereof to one end of the column sense line 103m and at the positive-phase (+) input terminal thereof to a voltage supply line 106, a reference capacitance Cf connected between the negative-phase input terminal and the output terminal of the operational amplifier OP, and a reset switch Sb connected in parallel to the reference capacitance Cf. The voltage supply line 106 is selectively applied with a constant charging voltage Vc or a predetermined reference voltage Vref via a select switch SW.
A sample & hold circuit 107m is connected at the input terminal thereof to the output terminal of the sensing circuit 105m, namely, to the output terminal of the operational amplifier OP. The sample & hold circuit 107m includes a sampling switch Ss and column select switch Sc connected in series between the output terminal of the sensing circuit 105m and an output signal line 108, and a hold capacitance Ch connected between a common junction Q between the switches Ss and Sc and the ground potential. Signal output from the sample & hold circuit 107m is delivered at the output signal line 108 via an output buffer 109.
Because of the circuit construction, the sensing circuit 105m provides a following output voltage Vsns:Vsns=−(Cs/Cf)×ΔV where Cs is a capacitance to be sensed and ΔV is a charging voltage to the capacitance Cs. As will be evident from the above expression, the charging voltage ΔV to the sense electrode 101 should be increased or the reference capacitance Cf should be decreased in order to raise the sensitivity of sensing the capacitance Cs.
Next, an example of the charge charging method will be described with reference to the circuit diagram in FIG. 4 showing the principle of the method.
As shown in FIG. 4, row drive lines 111 and column sense lines 112 are laid in the form of a matrix in relation to the sense electrodes 101 laid in the form of an array. A source-follower Nch MOS transistor Q1 and an Nch MOS transistor Q2 to select a row are connected in series between a power line 113 and a column sense line 112. The MOS transistor Q1 is connected at the gate thereof to the sense electrode 101, and the MOS transistor Q2 is connected at the gate thereof to the row drive line 111.
A Pch MOS transistor Q3 and charging current source Ic are connected in series between the power line 113 and the ground potential. The MOS transistor Q3 is connected at the gate thereof to a reset line 114. The common junction P of the MOS transistor Q3 and the charging current source Ic is connected to the sense electrode 101 via an Nch MOS transistor Q4. The MOS transistor Q4 is connected at the gate thereof to a charge control line 115.
The sensing circuit constructed as above is provided for each sense electrode 101, namely, for each sensor cell. The sensing circuit operates as will be described below with reference to the timing chart in FIG. 5.
First, supplied with a row drive signal RAD having a high level (will be referred to as “H level” hereinafter) via the row drive line 111, the MOS transistor Q2 is turned on. Then, supplied with an H-level charge control signal CEN via the charge control line 15, the MOS transistor Q4 is turned on. Thus, a row is selected.
Simultaneously with this row selection, the MOS transistor Q3 is supplied with a reset signal XRST having a low level (will be referred to as “L level” hereinafter) via the reset line 114 and thus turned on. Thereby, the voltage at the sense electrode 101 (will be referred to as “sensed voltage” hereinafter) VS is reset to a source voltage VDD which is a reference voltage. Thereafter, the reset signal XRST changes to H level, so that the MOS transistor Q3 is turned off. Thus, charging of the sense electrode 101 with a charge by the current source Ic via the MOS transistor Q4 is started.
After a constant time Tc, the charge control signal CEN changes to L level and thus the MOS transistor Q4 is turned off. Thus, the charging of the sense electrode 101 with the charge is complete. A variation of the voltage on the sense electrode 101 after the resetting will be taken as a sensed voltage Vsns. It is connected to the column sense line 112 via the source-follower MOS transistor Q1 and row-select MOS transistor Q2, and delivered to the outside via the column sense line 112.
The sensed voltage Vsns will be as follows:Vsns=(Ic×Tc)/Cs where Ic is a charge current to the capacitance Cs and Tc is a time of charging to the capacitance Cs. As will be evident from this expression, a reference charge (Ic×Tc) should be set small to increase the sensitivity of sensing the capacitance Cs within a limited dynamic range of the sensed voltage Vsns.
For an increased sensitivity of sensing the capacitance Cs in the voltage charging method, the charging voltage ΔV to the sense electrode 101 should be increased or the reference capacitance Cf should be small, as mentioned above. However, the charging voltage ΔV is limited by the source voltage to the apparatus, and, as the reference capacitance Cf is decreased, a disturbance noise or a circuit-operation noise will have an increased influence on the capacitance, resulting in a worse S/N (signal-to-noise) ratio. Also, for example, when an AC charge noise having an amplitude ΔQn takes place, the reference capacitance will have a noise charge of ΔQn added thereto in the worst case, which depends upon the charge and timing of sensing. The noise voltage will be ΔQn/Cf when converted into a voltage output from the sensing circuit 105m. When the reference capacitance Cf is decreased, the noise voltage will be higher, resulting in a worse S/N ratio.
On the other hand, in the charge charging method, setting the reference charge (Ic×Tc) smaller permits an increase in the sensitivity of sending the capacitance Cs within a limited dynamic range of the sensed voltage Vsns. However, when an AC charge noise having an amplitude of ΔQn takes place, the reference charge (Ic×Tc) will have a noise of ΔQn added thereto in the worst case. At this time, the S/N ratio is ΔQn/(Ic×Tc), and setting the reference charge (Ic×Tc) smaller will result in a worse SIN ratio.
Actually, when the aforementioned fingerprint sensor is installed in an electrical appliance such as a notebook personal computer (PC), since such an appliance is generally applied with a DC voltage from an AC source via a switching power source, a switching noise from the switching power source is superposed on an internal source voltage. Therefore, the switching noise will be an asynchronous disturbance noise, causing the worse S/N ratio and malfunction of the fingerprint sensor (capacitance sensor). That is, both the above two sensing methods, voltage charging and charge charging, are not advantageous in that they are limited in improving the sensitivity of sensing the capacitance and vulnerable to asynchronous disturbance noise.